Product Summary

The P89V51RD2FBC is an 80C51 microcontroller with 64 kB Flash and 1024 bytes of data RAM. A key feature of the P89V51RD2 is its X2 mode option. The design engineer can choose to run the application with the conventional 80C51 clock rate (12 clocks per machine cycle) or select the X2 mode (6 clocks per machine cycle) to achieve twice the throughput at the same clock frequency. Another way to benefit from this feature is to keep the same performance by reducing the clock frequency by half, thus dramatically reducing the EMI.

Parametrics

P89V51RD2FBC absolute maximum rating: (1)Tamb(bias) operating bias ambient temperature: -55 +125 ℃; (2)Tstg storage temperature range: -65 +150 ℃; (3)VEA voltage on EA pin to VSS: -0.5 14 V; (4)Vn DC voltage on any pin to ground potential: -0.5 VDD + 0.5 V; (5)Vit transient voltage (<20 ns) on any other pin to VSS: -1.0 VDD + 1.0 V; (6)IOL(I/O) maximum IOL per I/O pins P1.5, P1.6,P1.7: - 20 mA; (7)IOL(I/O) maximum IOL per I/O for all other pins: 15 mA; (8)Ptot(pack) total power dissipation per package Tamb = 25 ℃: 1.5 W.

Features

P89V51RD2FBC features: (1)80C51 Central Processing Unit; (2)5 V Operating voltage from 0 to 40 MHz; (3)64 kB of on-chip Flash program memory with ISP (In-System Programming) and IAP (In-Application Programming); (4)Supports 12-clock (default) or 6-clock mode selection via software or ISP; (5)SPI (Serial Peripheral Interface) and enhanced UART; (6)PCA (Programmable Counter Array) with PWM and Capture/Compare functions; (7)Four 8-bit I/O ports with three high-current Port 1 pins (16 mA each); (8)Three 16-bit timers/counters; (9)Programmable Watchdog timer (WDT); (10)Eight interrupt sources with four priority levels; (11)Second DPTR register; (12)Low EMI mode (ALE inhibit); (13)TTL- and CMOS-compatible logic levels.

Diagrams

P89V51RD2FBC block diagram

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P89V51RD2FBC
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Data Sheet

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P89V51RD2FBC,557
P89V51RD2FBC,557

NXP Semiconductors

8-bit Microcontrollers (MCU) 80C51 64K FL / 1K RM

Data Sheet

Negotiable